In systems that use clock signals produced by one integrated circuit to serve a second integrated circuit, supply current is unnecessarily high when active clock signals are transmitted to the second integrated circuit during intervals when the circuits on the second integrated circuit do not require an active clock signal. For example, in many GSM mobile station designs, a master clock produced by a digital baseband processor (DBB) serves functional blocks on the analog baseband processor (ABB). The master clock could be kept continuously active but this would be quite inefficient. When no ABB circuits require an active master clock signal, the master clock signal should be disabled to minimize supply current. One approach is to disable the clock signal within the ABB using well-known clock-gating techniques. This approach is not very effective because it does not limit the activity of the clock signal transmitted from the DBB to the ABB. Supply current is required to charge and discharge the capacitance of the line carrying the clock signal from the DBB to the ABB. The clock signal cannot be effectively controlled using DBB software because the DBB is a multitasking, multiprocessor device that may not be able to respond quickly when the clock signal is not needed by the ABB. Clock activity could be controlled using dedicated timing circuits, tailored to the ABB, on the DBB but this would be inflexible and would require additional circuitry.